1. Field of the Invention
The present invention relates to a frequency multiplier and, in particular, to a power composed type frequency multiplier.
The power composed type frequency multiplier is used for a local oscillator or a multiplier of a transmitting radio frequency (RF) in the microwave or millimeter wavelength range. In the power composed type frequency multiplier, the frequency multiplication is performed by: dividing the input signal into two divided signals each having half the power of the input signal; multiplying the input frequency of the divided signal respectively; and composing the power of the divided signals into output power of an output signal of the power composed frequency multiplier, specified by the multiplied frequency so that the output power is approximately the same as the input power.
2. Description of the Related Art
At the RF in the microwave or millimeter wavelength range, the frequency multiplication is performed by using a non-linear element and a micro strip line connected with the non-linear element. FIG. 1 is a schematic block diagram of a typical frequency multiplier 101 for such RF. The frequency multiplier 101 includes an FET 112 used as the non-linear element and a micro strip line (MS) 113 connected with FET 112. An input signal specified by a frequency "f" is sent to a gate electrode G of FET 112 through a matching network (MN) 111. The input signal is amplified by FET 112, producing an output signal from its drain electrode D to MS 113.
The MS 113 consists of an MS 113a and an MS 113b connected with MS 113a at a point Q located a quarter wavelength (.lambda./4) of frequency f far from an entrance of MS 113a. MS 113b has an open stub at .lambda./4 far from point Q. Therefore, when the output signal from the drain electrode D specified by frequency f is transmitted toward point Q through MS 113a, the output signal is reflected back to the drain electrode D, at point Q because of the open stub of MS 113b. As a result, the reflected signal and a succeeding output signal from the drain electrode D are combined at the drain electrode D in-phase and added to a source electrode (S) of FET 112 as an excessive signal for FET 112. This results in the saturation of FET 112, so that higher harmonics such as second harmonics (2f) and third harmonics (3f) are generated in FET 112. Since point Q acts as an open strip line for frequency 2f, the 2f signal is directly transfered to an MN 114 through point Q, but the 3f signal is reflected back to the drain electrode D at point Q, as well as fundamental frequency f. Because point Q act as a short strip line for the 3f signal only, the 2f signal is extracted from frequency multiplier 101 through MN 114.
Though frequency multiplier 101 includes FET 112, FET 112 is used only as the non-linear element for obtaining the higher harmonics. The power gain cannot be expected to be obtained from FET 112. Generally, in an RF in the microwave or millimeter wavelength range, it is difficult to realize RF generation or amplification by a semiconductor device due to technology and costs. Therefore, the power composed type frequency multiplier is very important as a last stage for RF generation. As a result, it is important to protect the power gains from being reduced due to the effect of frequency multiplication. The power composed frequency multiplication process accomplishes this purpose.
In the power composed type frequency multiplier, the following way is used for the frequency multiplication generally: an input signal specified by an input frequency f is divided into two divided signals each having half the power of the input signal; the frequency multiplication is performed to the divided signals respectively so that the input frequency of each divided signal is multiplied to, for example, 2f; and the divided signals specified by 2f respectively are composed so as to produce the output signal of the power composed type frequency multiplier specified by 2f and having output power approximately the same as the power of the input signal.
Wherein, in order to distinguish the frequency multiplier not performing power composition from the power composed type frequency multiplier, the frequency multiplier, such as the frequency multiplier 101 shown in FIG. 1, will be called "usual frequency multiplier" hereinafter.
FIG. 2 is a block diagram for illustrating a power composed type frequency multiplier 200 in the prior art. In FIG. 2, reference numerals 101a and 101b are the usual frequency multipliers each being the same as the usual frequency multiplier 101 in FIG. 1, except that step recovery diodes or varactor diodes 23a and 23b are used as the non-linear elements. In order to divide and compose power, well known Wilkinson type hybrid couplers (HYBs) 121 and 125 are used, respectively, and usual frequency multipliers 101a and 101b are provided between HYBs 121 and 125.
The Wilkinson type HYBs 121 and 125 are what are called in-phase hybrid couplers (IN-PHASE HYB). The IN-PHASE HYB 121 has a feature of producing two divided signals in-phase on their frequencies, and IN-PHASE HYB 125 has a feature of composing two input signals into a composed output signal when the two input signals are in-phase.
The IN-PHASE HYB 121 consists of: an input micro strip line having characteristic impedance Z.sub.0 and providing an input terminal 1; two .lambda./4 length micro strip lines having impedance (2).sup.1/2 .Z.sub.0 and providing output terminals 2 and 3 respectively; and a terminating resistor R having resistance of 2 Z.sub.0, provided between the output terminals 2 and 3. The IN-PHASE HYB 125 is also the in-phase hybrid coupler having construction the same as IN-PHASE HYB 121. The power composed type frequency multiplier 200 is for doubling an input frequency f, so that a composed output signal from IN-PHASE HYB 125 is specified by 2f.
In FIG. 2, when an input signal S.sub.in (f) specified by input frequency f is input to input terminal 1, the power of S.sub.in (f) is divided into two halves output from output terminals 2 and 3, respectively, so as to be in-phase with each other. The output signals from output terminals 2 and 3 are sent to usual frequency multipliers 101a and 101b in which frequency f of the output signals from output terminals 2 and 3 are doubled respectively. The usual frequency multiplier 101a consists of: MN 111a the same as MN 111; a step recovery diode or a varactor diode 112a used as the non-linear element same as FET 112; and MN 113a including a micro strip line the same as MS 113 and a matching network same as MN 114 in FIG. 1. The constitution and function of usual frequency multiplier 101b are same as those of usual frequency multiplier 101a. Therefore, usual frequency multipliers 101a and 101b produce frequency multiplied output signals specified by multiplied frequency 2f in-phase.
The frequency multiplied output signals from usual frequency multipliers 101a and 101b are sent to input terminals 4 and 5 of IN-PHASE HYB 125. The construction and function of IN-PHASE HYB 125 are the same as those of IN-PHASE HYB 121 except that the flow of signals is reversed to that in IN-PHASE HYB 121, so that the power of the input signals to IN-PHASE HYB 125 specified by frequency 2f in in-phase is composed by IN-PHASE HYB 125 so as to produce an output signal S.sub.out (2f) specified by frequency 2f.
However, when reflected signals are reflected back to terminals 2 and 3 of HYB 121 from usual frequency multipliers 101a and 101b respectively, some of the reflected power is absorbed in terminating resistor R, but the rest of the reflected power appears at input terminal 1 in-phase because of the characteristics of the in-phase hybrid coupler, which results in making the input impedance of power composed type frequency multiplier 200 unstable, producing power loss. Wherein, the power reflection cannot be avoided occurring at usual frequency multipliers 101a and 101b because the device impedance of diodes 112a and 112b changes corresponding to the change of the input level to diodes 112a and 112b. The same power reflection occurs in the case of an FET, such as FET 112 in FIG. 1. That is, when FET 112 is saturated, the reverse isolation S.sub.12 kept between the drain electrode D and G is fails. As a result, the power reflected from open stub 113b flows to the gate electrode G through the drain electrode D and appears at the input terminal of usual frequency multiplier 101 through MN 111. Therefore, the reflected power is reflected back to the in-phase type hybrid coupler from the usual frequency multiplier, including the FET.
Similar to the case of IN-PHASE HYB 121, the power loss is produced due to IN-PHASE HYB 125. When the reflected signal is reflected to IN-PHASE HYB 125 from a succeeding circuit, not depicted in FIG. 2, of power composed frequency multiplier 200, the reflected signal makes the output impedance of IN-PHASE HYB 125 unstable similar to IN-PHASE HYB 121, which causes IN-PHASE HYB 125 to exhibit a power loss.
As stated above, in the power composed type frequency multiplier in the prior art, Wilkinson type HYBs have been used for dividing and composing the power. This is because the Wilkinson type HYB is easy to use because the Wilkinson type HYB is an in-phase type HYB. However, applying the in-phase type HYB to the input and output HYBs respectively, causes occurrence of input and output impedance mismatch, producing a large power loss due to the frequency multiplication. This has been a problem in the prior art.